1. Technical Field
Embodiments of this invention relate to the field of memory controllers to read and write to a memory.
2. Description of the Related Arts
Current Double Data Rate (“DDR”) and Double Date Rate-II (“DDR-II”) Dynamic Random Access Memory (DRAM) subsystems exhibit significant latency when performing back-to-back reads to the same bank in memory. Several server chipsets can operate within a single rank of memory, providing a total of 4 independent memory banks. The probability of random traffic hitting the same bank repeatedly in such configuration is 1:4 (25%). In the case of page empty accesses (which are typical in server chipsets), the total bank conflict time is the total of the “activate to read” (tRCD) latency plus the “read to pre-charge” (tRPD) latency plus the “pre-charge” to “activate” (tRP) latency, or the “activate to activate command period” (tRC), whichever timing constraint is longer. In the case of DDR-266, Intel DDR-266 JEDEC Specification Addendum, Rev. 09, published Aug. 14, 2001, this bank conflict duration is typically 65 ns. In the case of DDR-II-533, published Jun. 25, 2001, this bank conflict duration is typically 60 ns. In contrast, the total data latency for a burst of 4 (32 bytes) for each memory technology is only 15 ns and 7.5 ns, respectively.
Traditional read-write switching methods prioritize read requests until the write requests queue up to a preset threshold. Then, an amount of write requests are “drained” back-to-back, and priority returns to the read requests (which are queued while waiting for the writes to drain). However, such read-write switching methods are slow and inefficient because no additional reads or writes are executed during the bank conflict duration.